Our client is a publicly listed semiconductor technology firm that is expanding there operations in Singapore and is looking for talented engineers to join the team.

Role

In your role as a Staff CAD Engineer (Infrastructure), you will support and improve CAD design tool usage and flows. Projects will have high visibility with a world-wide team of development engineers. This position emphasizes EDA compute infrastructure. You will play a critical role in improving the engineering compute infrastructure for efficiency and scalability.

Key Responsibilities

• Manage the EDA infrastructure and create/develop system monitors to support custom analog-mixed signal and digital design projects
• Implement best-in-class CAD license and hardware resource monitors.
• Develop benchmark and QA systems to qualify flows and to improve datacenter hardware specifications.
• Enhance EDA tool performance through optimization of compute (CPU, GPU) and storage architectures.
• Develop strategies for using load balancing and methodologies for bursting peak workloads into private cloud datacenters.
• Actively participate in CAD infrastructure planning with IT to improve productivity.
• Support tool bugs and issues, working closely with world-wide design teams and EDA vendors.

Basic Qualifications

• B.S. or M.S. in electrical/computer engineering or related engineering disciplines. Relevant work experience in industry commensurate to the title.
• Expert level understanding of Linux system and tools, as well as tcl/csh/bash scripting.
• Expertise in Python and Python/Qt GUI programming.
• High-level communication and organizational/execution skills to effectively drive CAD projects and priorities with Credo design teams and design tool vendors.

Expertise in Cadence, Siemens, and/or Synopsys EDA tool solutions. Good technical understanding of EDA design flows in one or more of the following areas - RC extraction, physical verification, analog simulators (especially for high-frequency RF designs), packaging tools and SI/PI analysis, RTL design/optimization/verification, SOC physical design.