We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME's advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME's heterogeneous integration platform.

Job Description:

Digital IC Design and system-level exploration:

• Contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.
• Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.
• Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.
• RTL implementation for custom circuit design using Verilog/SystemVerilog
• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architectures.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Prepare detailed design documentation, including specifications, test plans, and reports.

Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements:

• Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.