Join us in shaping the future of high-performance computing. We are a cutting-edge semiconductor company developing next-generation server-class SoCs for data centers, cloud computing, and AI acceleration, leveraging advanced CPU architectures and state-of-the-art interconnect technologies.

We are seeking an experienced Server Chip Architect to define and drive the architecture of innovative, scalable, and power-efficient CPU solutions. In this role, you will collaborate across hardware, software, and verification teams to bring world-class server processors from concept to production.

Key Responsibilities

• Define high-level architecture and hardware specifications for CPU subsystems, interconnects, memory systems, and accelerators.

• Develop detailed hardware architectural specifications in close collaboration with digital design engineers, ensuring alignment with power, performance, and timing goals.

• Provide technical leadership across the development cycle, working with design, verification, and system validation teams to resolve architectural and implementation issues efficiently.

• Review and refine verification and validation plans, identify coverage gaps, and support debugging in pre-silicon and post-silicon phases to ensure compliance with specifications and standards.

• Evaluate existing hardware modules, identify opportunities for performance, scalability, and efficiency improvements, and drive architectural enhancements.

• Collaborate with firmware, software, and system engineering teams to ensure seamless integration of hardware features into the overall server platform.

Job Requirements

• Bachelor's degree or above in Electrical Engineering, Computer Engineering, or a related field, with 8+ years of industry experience in CPU or SoC architecture design.

• Proficient in DDR system architecture design and implementation, familiar with DDR4/DDR5/LPDDR5 protocols.

• Hands-on post-silicon validation and performance tuning experience, with the ability to analyze and optimize memory subsystem performance.

• Deep understanding of AXI/ACE/CHI bus protocols.

• Experienced with different Network-on-Chip (NoC) architectures and their characteristics.

• Proven track record in large-scale SoC NoC planning and performance analysis.

• In-depth knowledge of CPU microarchitecture, cache hierarchy, coherency protocols, and interconnect fabrics (e.g., CCIX, CXL, NoC).

• Skills in correlating NoC structures with DDR features to analyze SoC bandwidth ,

• Prior experience in SoC performance bottleneck identification and optimization is highly preferred.

• Knowledge of embedded processors and firmware operation, as well as processor subsystems such as ARM Cortex-A/M/R or RISC-V, is a strong plus.