In your new role you will:

• Generate DFT instruments with advanced EDA tools, including MBIST, OCC, TAP controller, BoundaryScan, LBIST, SSN and other DFT instruments.
• Perform DFT instruments integration and verification of test functions with industrial simulation tools and in-house verification tools.
• Perform Block level and chip level ATPG Scan Compression integration, DFT rule checking and debugging for various testing modes.
• Generate and verify test patterns with flow of automation.
• Assist test pattern debugging on ATE machine and carry out failure analysis.
• Research on advanced DFT techniques for Automotive Ethernet products.

You are best equipped for this task if you have:

• Bachelor's/Master's Degree in Electronics/Electrical Engineering or related fields with coursework in digital logic design, computer architecture.
• 3 ~10 years or more of hands-on experience in digital DFT design, logic simulation, synthesis, formal verification, ATE test and silicon failure analysis.
• Solid knowledge and background in ASIC development.
• Proficiency in Linux shell scripting and scripting languages such as Perl, Python, Tcl, and Make.
• Having passion in technology; being flexible, goal-oriented, and team player.
• Excellent verbal and written communication skills.
• Rank of position will be offered based on candidate's level of skill, knowledge and experience.