The High Energy Efficiency Chip design group is looking for a talented and enthusiastic Logic Designer to join our growing team and take part in developing state-of-the-art products. You will be working with the latest silicon technologies and processes to build the most advanced large-scale complex designs. As part of this role, you will lead the full development cycles of design units from architecture to tape-out. And work in full collaboration with the architecture, validation, Backend, IC operation, Software, and ASIC teams.

Join us and contribute to our growing success in the High Energy Efficiency world.

Responsibilities :

• Participate in IP selection and architecture definition, formulate functional specifications.
• Participate in PPA evaluation & Optimization.
• Developing functional block/unit RTL for architectural features and optimizing for power, area, and timing
• Support debug for RTL simulation, gate-level & post-level simulation
• Perform all aspects of quality checks base-on FE eda tools like Spyglass.lint/cdc/rdc etc.
• Support all aspects of design flow from logic synthesis, power, timing, quality checks
• You will take ownership on all project steps, from Arch --> production.

Qualifications:

• At least 5 years of experience in ASIC design
• Design Experience with logic FE tools(Vcs,verdi,spyglass,DC, etc.)
• Physical Design knowledge or experience is very helpful
• Design Experience with Static Timing Analysis is a PLUS
• Prefer experience with hands-on implementation of advanced-process chips
• Prefer experience with low-power design and power-simulation
• Proficiency in Tcl, Perl, is PLUS
• Prefer experience with multiple tape-out and chip bring-up test
• Prefer experience with management capabilities is PLUS.