Job Description:

As an Analog Mixed-Signal IC Layout Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include floor planning, creating layout of building blocks and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, antenna rule on top of DRC and LVS. The company seeks a highly motivated and team orientated individual to work with both layout and design engineers across multiple time zone.

Basic Qualifications:

• Bachelor or advanced Diploma degree in EE

Required Experience:

• 2+ years of experience developing layout for highspeed analog IC designs in finFET technology
• Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for highspeed circuits
• EMIR and antenna DRC rules aware layout practices
• Experience writing SKILL and TCL scripts is highly recommended