As a NAND Technology Integration (NTI) senior engineer within our Technology Development Group at Micron Technology, you will be part of a word-wide team responsible for driving NAND technology from R&D to high volume manufacturing. You will be responsible for leading a multi-disciplinary team of engineers to deliver industry leadership for performance and cost with fast-paced timelines.

Expectations:

• Lead process development and integration of disruptive modules in areas of advanced interconnect for next generation NAND technology.
• Derive construction specifications based on electrical specification requirements and response, inline metrics, unit processes capabilities and design rules
• Design, execute and analyze experiments necessary to meet engineering specifications based on structure to electrical correlations
• Solve problems with a model-based approach and drive technical innovation through process improvements, patents and/or technical papers
• Proficient in data analysis through JMP, Python or other data engineering software and presentation of this data with recommendations
• Transfer of technology to High Volume Manufacturing (HVM) fab, drive process improvements for yield and cost maturity

Qualifications:

• Minimum five years' experience in semiconductor memory processes, integration, and strong technical skills with demonstrated success in engagement with worldwide teams
• Prior integration experience in development of advanced interconnect modules and cross-functional project management experience
• Familiarity with NAND architecture, process, operation, cell, testing, and design
• In-depth knowledge of semiconductor device physics, semiconductor reliability requirements and failure mechanisms, and electrical characterization methods including detesting for functionality, defect classification and reliability
• Prior experience and expertise in defining semiconductor products' electrical specification requirements, deriving and setting structural specifications, and driving unit process development to meet the product requirements
• Must have demonstrated the ability to conceptualize and set-up new process integration flow, detect and resolve inline defectivity issues, and solve problems across multi-functional groups.
• In-depth knowledge of Design of Experiments, statistical process control (SPC), advanced JMP data analysis skills, electrical device analysis and correlation analysis of electrical response to inline metrics
• Expertise in Failure Mode and Effects Analysis (FMEA) method and concepts with prior experience in applying the techniques to proactively prevent product failures
• Prior experience in technology transfer to HVM fab, yield ramp and process cost optimization
• Strong interpersonal, oral and written English communications-skills

Education:

M.S. in Electrical Engineering, Microelectronics, Physics, or Material Science Engineering, PhD preferred Or Equivalent work experience