Job descriptions :

1. Work with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Responsible for backend/PD tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape-out.

3. Research the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Job requirements:

• Bachelor's degree or above in electronic engineering, microelectronics, or computer science.

• At least Three (3) years of work experience in Place & Route. Hands-on project experience at advanced technology is required.

• Strong communication ability, good confidence and self-motivation.

- Willing to work overtime and external communication are required.

- One day off per week, with non-fixed rest days.

What we offer:

• Competitive salary package

• Medical insurance (including dental)

• Annual Health Screening

• Company trip & teambuilding activities