We are seeking a highly motivated digital IC designer with strong expertise in high-performance digital design/compute for AI and system-level architecture modeling to join our Heterogeneous System Design Team. The successful candidate will play a key role in the architecture exploration, co-optimization, and implementation of multicore and multi-chip systems, working closely with IME's advanced packaging and heterogeneous integration teams. This role offers a unique opportunity to shape next-generation compute platforms by jointly optimizing architecture, packaging, thermal, power, and interconnect considerations using IME's state-of-the-art heterogeneous integration technologies.

Job Description:
Digital IC Design and system-level exploration:

• Contribute to the architecture, design, and development of advanced digital integrated circuits, ensuring compliance with performance, power, area, and functionality requirements.
• Perform system-level modeling, simulation, verification and validation to guide architectural trade-offs and optimize end-to-end system performance.
• Translate system and algorithm requirements into efficient digital architectures, with particular emphasis on scalability and energy efficiency.
• Implement RTL designs using Verilog/SystemVerilog, following best practices for correctness, reusability, and verification readiness.
• Derive detailed block-level specifications and design highly optimized custom digital building blocks, including but not limited to:
  
  Systolic arrays and dataflow engines
  Datapath controllers and schedulers
  Integer and floating-point processing units
  FFT and signal-processing accelerators
  Apply Edge AI design principles to enable low-latency, energy-efficient inference and signal processing close to the data source.

Work closely with the advanced packaging and integration teams to perform thermal modeling and analysis, and translate thermal constraints into optimized floorplanning, power distribution, and timing closure strategies for digital compute chips.

Simulation, Verification, and Implementation:

• Conduct thorough simulation and verification of digital designs to validate functionality and performance.
• Perform timing analysis and collaborate with the team to optimize designs for timing closure.
• Contribute to power analysis activities and implement power-efficient design techniques.
• Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

Publication:

• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.
• Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture
• Prepare detailed design documentation, including specifications, test plans, and reports
• Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues
• Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.