About the Company

Our client is a next-generation semiconductor and AI computing company building a breakthrough architecture that dramatically reduces the energy consumption, latency, and cost of AI workloads. Our proprietary memory-compute technology enables high-efficiency neural processing suitable for edge devices, IoT systems, and large-scale AI deployments.

You will be joining a world-class team of IC designers, architects, and software engineers working at the frontier of computing innovation - developing hardware that will reshape the future of AI.

Responsibilities

• Collaborate closely with design engineers and chip architects to define, document, and implement detailed test plans for SoC design verification.
• Build and maintain verification infrastructure and automated environments for validating SoC architecture, functional correctness, and performance.
• Develop reusable testbenches, behavioral models, and constrained-random or directed test cases for block-level and system-level verification.
• Establish regression strategies, verification methodologies, and supporting scripts/tools. Drive functional coverage measurement and closure for design releases and tape-out.
• Work with RTL design engineers to debug and identify root causes of simulation failures and verification gaps.
• Support test engineering teams during post-silicon validation, including test bring-up and debugging activities.
• Mentor, guide, and coach junior engineers while driving improvements in verification efficiency and methodology across the team.

Requirements

• Master's degree with 8+ years of relevant experience, or PhD with 3+ years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Deep expertise in UVM/OVM, semiformal verification, assertion-based verification, and hardware/software co-verification methodologies.
• Strong experience developing verification infrastructures, test plans, coverage analyses, and testbench/testcase development for functional and performance verification.
• Proficiency in Verilog, SystemVerilog, scripting languages (Python/Perl/TCL/Shell), C/C++, SystemC, and ISA-level assembly coding.
• Familiarity with industry bus protocols and architectures such as MIPI, AMBA (APB/AHB/AXI), RISC-V, ARM, and DSP cores.
• Experience verifying designs at both the RTL level and post-place-and-route (gate-level) simulations.
• Demonstrated ability to work in a fast-paced startup environment, independently and collaboratively, while providing technical leadership to team members.

Preferred (Good-to-Have) Experience

• Knowledge of AI/ML computing architectures, GPUs, ISPs, or accelerator-based compute systems.
• Experience verifying mixed-signal designs or digital-analog interfaces.
• Exposure to verification of high-speed I/O such as PCIe, DDR, or similar interfaces.

Why Join?

• Shape the future of AI hardware: Contribute directly to a disruptive computing platform that delivers significant gains in energy efficiency and real-world AI performance.
• Work with world-class engineers: Collaborate with deeply experienced IC designers, architects, and technologists solving some of the hardest problems in modern computing.
• Cutting-edge technology: Gain hands-on experience with next-generation SoC architectures, AI accelerators, mixed-signal systems, and advanced verification methodologies.
• Career growth: Multiple seniority levels available, with opportunities for mentorship, technical leadership, and pathway advancement.
• Innovative startup culture: Fast-moving environment where your ideas matter, contributions are visible, and creativity is encouraged.
• Competitive compensation: Attractive salary, performance incentives, benefits package, and a supportive environment that rewards excellence.
  
  License No.22C1076 | EA Reg.: R22108987