As a Back-End IC Engineer, you will apply the latest design methodology and milestone flow to deliver state-of-the-art design over advanced technology node from RTL to GDSII. You should have very good experience in layout activities of block and level, including floor-

planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities

1. Understanding of SoC for top-down/bottom-up physical design integration in advanced technologies.

2. Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows.

3. Must have knowledge of P&R, Extraction, Physical Verification, STA, ECO.

4. Build automation flows wherever needed/adapt to existing flows for re-use.

Key Qualifications

1. A Master's Degree in EE, CS, Math, Physics or related subjects, PhD preferred.

2. A deep understanding of backend digital design flow.

3. Proficient in timing constraints, physical constraints.

4. Proficient in handling EDA tools across floorplan/partition/placement/CTS/route stages for SoC top-level.

5. Proficient with backend EDA tools Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PrimeTime, PrimeRail/Voltus, Redhawk

Preferred Qualifications

1. Proficiency in scripting languages (e.g., Tcl, Perl)