You will be joining in a member of an expert R&D team that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits built for AI markets.

Responsibilities

1. Enhancing and expanding the existing tools' architecture to cover timing analysis.

2. Creating new frameworks for analysis of effects dominant at 5nm and below.

3. Using machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutions.

4. Characterize the standard cell library for custom PVT base on foundry kit at 5nm and below.

Key Qualifications

1. A Master's Degree in EE, CS, Math, Physics or related subjects, PhD preferred.

2. Experience in EDA tools and one or more of transistor-level timing, power, noise, aging, reliability, and EMIR analysis.

3. Experience in development of circuit simulation or library characterization programs.

4. High-level understanding of SPICE simulation transistor models and gate-level schematics.

Preferred Qualifications

Proficiency in scripting languages (e.g., Tcl, Perl)