Job Description:
We are looking for a highly skilled Physical Chip Design Engineer to lead the development of low-power and high-performance chip design processes. This is a critical role that requires deep expertise in advanced semiconductor technologies and the ability to drive full-chip physical design workflows from start to finish.

Key Responsibilities:

• Low-Power Physical Design Workflows: Lead and optimize processes to enhance energy efficiency while maintaining chip performance.
• Full-Chip Floor Planning & Place-and-Route: Oversee floor planning to ensure optimal performance, power, and area. Manage place-and-route processes for efficient, functional designs.
• Power Network Design & Analysis: Design and optimize power distribution networks, perform grid analysis to ensure power integrity and low-power design.
• Timing Closure, Power Integrity, & Signal Integrity: Resolve timing challenges, ensure power and signal integrity signoff, and perform necessary optimizations.
• Physical Verification (DRC & LVS): Conduct thorough physical verification, including Design Rule Checks (DRC) and Layout Versus Schematic (LVS) to ensure compliance with design specifications.

Qualifications:

• Education: Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Science, or related field. Advanced degrees (Master's/Ph.D.) are a plus.
• Experience: 4-5 years of hands-on experience in physical design, with expertise in low-power, high-performance chip design. Experience with 12nm and below semiconductor technologies and tape-out processes is essential.
• Technical Skills:
  • Expertise in full-chip floor planning, place-and-route methodologies, and physical verification (including DRC and LVS).
  • In-depth knowledge of power network design, IR drop analysis, and timing closure.
  • Proficiency in Synopsys IC Compiler, Cadence Innovus, or similar tools.
  • Proficiency with Static Timing Analysis (STA) tools.
• Programming Skills: Strong scripting skills in Perl, TCL, Python, and C++.