One of our US Global Semiconductor IC design is growing their design teams in Singapore.

Role : Design Verification Engineer (DV)

Location : Singapore

Experience : 3 to 7 years.

• Technical Requirements:

o Expert-level UVM and SystemVerilog verification

o Advanced coverage-driven verification methodologies

o Experience with complex SoC verification strategies

o Knowledge of ARM CPU verification techniques

o Understanding of high-speed interface verification (PCIe, USB, DDR)

o Formal verification and assertion-based verification

o Verification planning and test strategy development

o Team leadership and mentoring capabilities

• Key Responsibilities:

o Overall verification strategy and planning

o Test plan development and review

o Coverage goals and sign-off criteria definition

o Verification environment architecture

o Team coordination and quality oversight

o Final verification sign-off

EA licence : 14C7174

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