THE ROLE:

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's SERDES IP, resulting in no bugs in the final design.

THE PERSON:

The ideal candidate should have a deep understanding of analog design and able to lead, attend and present at design review meetings with teams worldwide.

KEY RESPONSIBILITIES:

• Circuit design of wireline transceiver building blocks (PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.)
• Conduct peer reviews of circuit design and verification results
• Working with validation team to evaluate silicon results

PREFERRED EXPERIENCE:

• Extensive experience with high speed analog design with blocks like ADC, PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer.
• Experience with latest process technologies like 7nm or below Finfet technology.

ACADEMIC CREDENTIALS:

• Bachelors/Masters/Phd Degree in Electronic Engineering

LOCATION:

Singapore