Job Responsibilities:

1. Lead the analog design and development of either DDR or PLL IP (select one focus area), and collaborate with cross-functional teams to complete the full IP development cycle.

2. Provide support for mass production and debugging of the assigned IP.

3. Participate in the development of other SerDes-related IPs and coordinate tasks related to product integration.

Requirements:

1. Master's degree or above in Electrical Engineering, Microelectronics, or a related field; minimum 5 years of experience in analog circuit design.

2. At least 3 years of hands-on experience specializing in DDR or PLL design, with proven ability to lead projects independently and substantial tape-out experience.

3. Experience with FINFET processes is a strong advantage.

4. Proactive, detail-oriented, responsible, with a positive work attitude and strong communication skills; team player with a collaborative mindset.