Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. This is a newly created position with the Singapore SOC Design Engineering team. There will be 2 headcounts for the team in Singapore.

Senior Staff / Staff DFT Engineer

Responsibilities:

• Own DFT implementation including scan insertion, boundary scan, MBIST, and ATPG for ultra-low power SoCs.

• Develop low-power DFT architectures and generate structural test vectors to improve coverage and reduce test cost/time.

• Perform pre- and post-layout scan and MBIST simulations.

• Collaborate with design teams on STA, physical, power, and logical DFT integration.

• Support test engineers in silicon bring-up and production test program development.

Requirements:

• BS/MS in ECE/EE with 10+ years of hands-on DFT implementation experience.

• Expertise in scan (Stuck-At, At-Speed, Path Delay), scan compression, MBIST, and boundary scan techniques.

• Strong experience in hierarchical and low-power DFT architecture for complex SoCs.

• Proficiency in test coverage/time analysis, RTL design, and scripting (Tcl); GLS experience preferred.

• Excellent communication skills, self-motivated with high attention to detail.

Interested applicants, kindly send in a copy of your updated resume in WORD document to hr@searchstaffing.com.sg stating your current and expected remuneration together with notice period required to current employer.

You can also contact Vincent Low for a confidential discussion at 6749 4236.

EA Personnel Registration No: R1324700