Broadcom Central Engineering is seeking a talented engineer to assist with the development, installation, and testing of physical verification decks (DRC/LVS), primarily within the Calibre environment, supporting advanced FINFET technologies.

Experience with Calibre and Virtuoso is essential, as the position requires the development of test designs. Programming skills in Perl, Python, TCL, SKILL, and UNIX shell languages are a plus. Knowledge of industry-standard EDA tools and their capabilities for physical verification is required.

Responsibilities:

- Develop and deploy Calibre DRC/LVS decks for advanced FINFET nodes.

- Define and create simple test cases and basic test structures to validate (QA) PV decks.

- Support existing automation using PERL, Python, and UNIX shell scripting.

- Create documentation and provide hands-on training for Design & Layout engineers as needed.

- Track and resolve tool and technology file issues by collaborating with foundry partners.

- Engage with EDA and Foundry R&D teams on advanced node capability roadmaps, identifying new tools, developing evaluation criteria and processes, and championing their introduction and usage within the Broadcom design community.

Requirements:

- Master's degree in Electrical Engineering or Computer Science plus 6+ years of EDA experience.

- User-level familiarity with related CAD Tools: Calibre, Virtuoso Layout & Schematics.

- Background in layout design and technology knowledge to help solve challenges in layout, physical verification, and post-layout extraction.

- Experience in all phases of CAD tools, including evaluation, QA, testing, release, user support, and documentation.

- Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team.