Principal Multi Project Wafer Engineer
- Work with customer and Foundry to fix DRC/LVS violation on MPW tapeouts.
- MPW Cluster Floor Plan Execution: Merge Customer designs, insert dice saw lanes and required Fab structures to ensure smooth Fab and die saw processing.
- Work with customer and Foundry team to ensure error-free mask creation and fab setup inputs. Manage release of merged MPW masks to Foundries for wafer fabrication.
- Establish, implement, document, and continuously improve processes and quality systems related to ensuring efficient and flawless MPW tapeouts.
- Degree in Electrical Engineering, Computer Science, and other relevant engineering disciplines with at least 5 years of Relevant Semiconductor experience supporting Semiconductor Fab
- Experience in semiconductor design environment and in depth understanding of tapeout flows and mask generation
- Solid knowledge on DRC/LVS/EDA
- LINUX/UNIX based script development and Web programming skills and Scripting Languages
- Experience with Cadence Virtuoso, Maskcompose, Quickview or similar tools
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV in MS Word format to Sansan Sanryani Cahaya EA 12C6130/R1767240. Shortlisted candidates will be contacted for a discussion.
HPS Partners Pte Ltd