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Senior DFT Engineer (Design For Testing) job in East at Experis Singapore

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Senior DFT Engineer (Design For Testing) at Experis Singapore

Senior DFT Engineer (Design For Testing)

Experis Singapore East Permanent
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Responsibilities
  • Advance Structural Test Patterns for multiple IPs
  • Accountable for target Structural test coverage for Digital logic, SRAMs and Mixed-Signal IPs
  • Design FPGA Logic to apply test patterns and improve the diagnostic capability
  • Scan/iJTAG/Memory BIST flow development, ATPG pattern generation, verification, and coverage analysis
  • Pre-silicon verification of DFT schemes and patterns using Industry standard tools
  • Diagnose and debug the pattern failures on ATE to root cause the problem
  • Work with Design Team and Product Engineering Teams to meet production schedule



Requirements
  • Master's or Bachelor degree in Electronics and Communications Engineering or equivalent
  • 2 to 5 years of working experience in DFT and ATPG
  • Knowledge of Fault modelling, Scan architecture, Scan compression and Memory testing techniques
  • Expertise with industry standard tools like TestKompress, DFT advisor, DFT Compiler
  • Experience in Gate Level Simulation and Debug
  • Good knowledge of Digital design and ASIC design flow
  • Good Knowledge of Verilog/ VHDL
  • Knowledge of Shel Scripting/ Perl/ C++ is a plus





Teh Hui Tian, Zoe EA License No. 02C3423 Personnel Registration No. R2089915

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